Electronic power device integrated on a semiconductor material and related manufacturing process

ABSTRACT

An electronic power device is integrated on a semiconductor substrate having a first conductivity type, on which an epitaxial layer of the same conductivity type is grown. The power device comprises a power stage and a control stage, this latter enclosed in an isolated region having a second conductivity type. The power stage comprises a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The control stage comprises a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage and the control stage to be entirely formed in the epitaxial layer.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. patent application Ser. No. 09/238,693, filed Jan. 27, 1999, now pending, which application is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to an electronic power device integrated on a semiconductor material.

[0004] The invention further relates to a manufacturing process for an electronic power device.

[0005] 2. Description of the Related Art

[0006] As is known, in the conventional technology used in the production of integrated power devices, for example VIPower type technology (VIPower is a trade mark of STMICROELECTRONICS S.r.I. and means vertically intelligent power) or the Smart power BCD type, the isolation between a power portion and a control portion comprised in the power device is produced by the known technique of junction isolation.

[0007] More particularly, this technology makes use of an epitaxial growth split in two distinct moments of the process sequence which leads to the production of the device.

[0008] The presence of a first epitaxial layer and of a second epitaxial layer overlapping the first is in fact useful for producing buried areas, having an opposite conductivity sign compared to that of the epitaxial layer, which will form areas of isolation including the control portions of the power devices.

[0009] This split epitaxial growth further allows the formation of buried areas having the same conductivity type as the epitaxial layer, but with different resistive values.

[0010] Although this known technical solution is advantageous as far as certain aspects thereof are concerned, it nevertheless presents certain drawbacks such as:

[0011] high production costs for the power device;

[0012] high dispersion of resistivity and thickness values (sometimes greater than 10%) and non-uniformity in growth on the slice of semiconductor material on which the device is integrated;

[0013] difficulty in alignment of the areas produced in the second epitaxial layer compared to those produced in the first epitaxial layer.

SUMMARY OF THE INVENTION

[0014] An embodiment of this invention is an electronic power device integrated in a semiconductor material, with structural and functional features able to overcome the limitations and/or drawbacks previously indicated with respect to the prior art.

[0015] The embodiment is directed to a process which allows for the production of improved electronic power devices, which in terms of electric performance and of space used, are better than the devices designed with the above mentioned known techniques.

[0016] The method produces electronic power devices without having to use the double epitaxial growth and instead uses an ion implantation at high energy.

[0017] The use of high energy ion implants does not lead to high costs in the processes of integration because the machinery used in manufacturing these is very productive, that is, the machinery is able to work a high number of slices of semiconductor material in a short time, and therefore is less expensive.

[0018] The features and the advantages of the invention will become clear from the following description of an embodiment thereof, which is herein set as example for descriptive and non limiting purposes, with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIGS. 1 to 9 show in temporal sequence the phases of the manufacturing process of a power device according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020] With reference to FIG. 9, an electronic power device 1 according to an embodiment of the invention comprises one power stage indicated with PT and one control stage indicated with CT.

[0021] Still referring to FIG. 9 the control stage CT includes a signal transistor T1 of NPN type and a lateral signal transistor T2 of PNP type.

[0022] For ease of exposure, the structure of device 1 will now be described with reference to the process phases of its manufacture.

[0023] Generally, for the production of the device 1 a substrate of semiconductor material 1A is used, for example silicon, having a first conductivity type, in particular N++.

[0024] An epitaxial layer 2 is grown on the substrate 1A having the same conductivity type, in particular N (FIG. 1).

[0025] It is as well to specify that the epitaxial layer 2 presents a concentration and a thickness which are suitably calibrated according to the class of voltage to which device 1 will have to operate.

[0026] Still referring to FIG. 1, an oxide layer 3 is then formed on the epitaxial layer 2.

[0027] After the removal of portions 4 of the oxide layer 3 (FIG. 2) and the growth of a first pre-implant oxide layer 5 (FIG. 3) on the corresponding portions of epitaxial layer 2 left uncovered, an ion implantation follows. The ion implantation is carried out with an energy comprised between 20 and 200 KeV and following diffusion of a dopant ions having a second conductivity type, in particular P, for creating surface contact areas 6 a, 6 b, 6 c, 6 d.

[0028] More particularly, the contact areas 6 a and 6 b form a surface contact base region of the power stage PT, whilst the surface contact areas 6 c and 6 d form a portion of surface contact of an isolation region IS which surrounds the control stage CT (FIG. 9).

[0029] A deposition of a first thin photoresist film 7 is performed and is followed by the removal of portions of the first pre-implant oxide layer 5 and of portions of oxide layer 3 not covered by the first thin photoresist film 7 (FIG. 4).

[0030] A second pre-implant oxide layer 9 is then grown (FIG. 5).

[0031] The removal of the first thin photoresist film 7 is then carried out.

[0032] Still referring to FIG. 5, the deposition of a second thin photoresist film 10 is then foreseen, followed by an ion implantation carried out at an energy comprised between 20 and 200 KeV and following diffusion of a dopant ions having a first conductivity type, in particular N+, in order to produce surface contact areas 11 a, 11 b, and 11 c.

[0033] More particularly, the area 11 a creates a surface contact emitter region of the power stage PT, whilst the 11 b and 11 c areas form a surface contact area including a surface contact collector region of the signal transistor T1 and an area of a surface contact base region of the lateral signal transistor T2.

[0034] After the removal of the second thin photoresist film 10, the deposition of a first thick photoresist film 12 having a thickness of about 6 μm is carried out, followed by an ion implantation at high energy greater than 3000 KeV and in doses of around 1013-1014 ion/cm2 and by a following diffusion of a dopant ions having a second type of conductivity type, in particular P, in the portions of epitaxial layer 2 not protected by the thick photoresist film 12, to form buried areas 13 a and 13 b at a depth of about 6 μm from an upper surface 20 of the epitaxial layer 2 (FIG. 6).

[0035] More particularly, still referring to FIG. 6, the buried area 13 a adjoining the surface contact base region completes a base region B of the power stage PT, having a preferably annular form as seen from the upper surface 20 of the device 1.

[0036] Furthermore, the buried area 13 b adjoining the portion of surface contact completes the isolation region IS and also preferably has an annular form.

[0037] After the removal of the first thick photoresist film 12, the deposition of a second thick photoresist film 14 then follows, with a thickness of 6 μm, followed by a further ion implantation of high energy greater than 3000 KeV and in doses of around 1014-1015 ions/cm2 and by a following diffusion of a dopant ions having a first conductivity type, in particular N+, in the portions of epitaxial layer 2 not protected by the second thick photoresist film 14, for the formation of buried areas 15 a and 15 b at low resistivity and at a depth of around 3-4 μm from the surface 20 (FIG. 7).

[0038] The buried areas 15 a and 15 b lay in part above respectively the buried areas 13 a and 13 b.

[0039] More particularly, the buried area 15 a adjoining the emitter surface region 11 a forms an emitter region E, preferably of annular form, of the power stage PT, while the buried area 15 b adjoining the surface contact area (11 a, 11 b) forms an area (CT1, BT2), also preferably of annular form, including a collector region CT1 of the signal transistor T1 and an extrinsic base region BT2 of the lateral signal transistor T2.

[0040] The annular emitter region E is enclosed in the annular base region B, whilst the annular area (CT1, BT2) is enclosed in the isolation region IS.

[0041] Subsequently, after the removal of the second thick photoresist film 14 and the deposition of a third thin photoresist film 16, an ion implantation is carried out with an energy comprised between 20 and 200 KeV and with a following diffusion of a dopant ions having a second conductivity type, in particular P, in the portions of epitaxial layer 2 not protected by the third thin photoresist film 16, to form an area (BT1, ET2, CT2), enclosed in the annular area (CT1, BT2), and including a base region BT1 of the signal transistor T1 and emitter ET2 and collector CT2 regions of the lateral signal transistor T2 (FIG. 8).

[0042] After the removal of the third thin photoresist film 16 and the deposition of a fourth thin photoresist film 17, a further ion implantation is carried out with energy comprised between 20 and 200 KeV and with a following diffusion of a dopant ions having a first conductivity type, in particular N, in the portions of epitaxial layer 2 not protected by the thin photoresist film 17, to form an emitter region ET1 of the signal transistor T1 (FIG. 9).

[0043] Finally, on the front surface of device 1 which is covered by a silicon dioxide layer with known photolithographic techniques of deposition, metal strips are formed which when in contact with the surface areas form the electrodes of the device itself.

[0044] In conclusion, the electronic power device 1, not needing a double epitaxial layer in order to be produced, leads to the elimination of all the drawbacks connected to the presence of this double layer (non-uniformity of thickness and resistivity in and between the slices of semiconductor material, difficulty in aligning the areas produced in the upper epitaxial layer as compared to those in the lower epitaxial layer).

[0045] Furthermore, the process for the production of the device 1, is therefore carried out in an extremely shorter working time, in that the use of ion implants at high energy allow for drastically reduced diffusion times.

[0046] The above cited process further allows for electronic power devices with electrically active crystallographic defect density which is practically negligible compared to that one obtained by using the known technique described above.

[0047] This improvement is actually due to the use of ion implantation at high energy which as is known causes damage (in any case totally recoverable) to the crystal only in the areas where the doping ion stops, whilst leaving the surface of the slice undamaged. Further, the process allows for the realization of electronic power devices with vertical and horizontal dimensions which are extremely reduced (for example a vertical control NPN transistor with the relative isolation area is produced in 5 μm thickness and has an overall dimension of ˜4×4 μm2 of active emitter area).

[0048] Finally, the process according to the invention allows for, in equal applications, electrical components having better features than those offered by prior art components (for example: transition frequency in the 109-1010 Hz field for control transistors of the NPN type, vertical power transistors of the NPN type with higher commutating speeds and/or with larger SOA (Safe Operating Areas).

[0049] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

1. An electronic power device integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer, of the first conductivity type, is grown, said power device comprising: a power stage PT and a control stage CT, the latter enclosed in an isolation region having a second conductivity type, said power stage PT comprising a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area, and having the first conductivity type, said isolation region and said control stage CT comprising respectively a third buried area, having a second conductivity type, and a fourth buried area, partially overlapping the third buried area and having a first conductivity type, wherein said first, second third and fourth buried areas are formed in the epitaxial layer at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layer.
 2. The power device according to claim 1, wherein said first and third buried areas are placed at a depth of about 6 μm from an upper surface of the epitaxial layer.
 3. The power device according to claim 2, wherein said second and fourth buried areas are placed at a depth of about 3-4 μm from the upper surface of the epitaxial layer.
 4. The power device of claim 1, further comprising: first, second, third, and fourth contact regions positioned in the epitaxial layer, the first and second contact regions extending from a surface of the epitaxial layer to contact opposite ends of the first buried area, and the third and fourth contact regions extending from the surface of the epitaxial layer to contact opposite ends of the third buried area.
 5. The power device of claim 4 wherein the second buried area is positioned between the first and second contact regions and the fourth buried area is positioned between the third and fourth contact regions.
 6. The power device of claim 1, further comprising first and second contact regions extending from a surface of the epitaxial region to contact opposite ends of the fourth buried region.
 7. The power device of claim 6, further comprising a doped region of the second conductivity type positioned in the epitaxial layer and between the first and second contact regions.
 8. The power device of claim 7, further comprising a doped region of the first conductivity type positioned in the doped region of the second conductivity type.
 9. The power device of claim 1, wherein the power stage PT includes: a surface contact region of the first conductivity type positioned in the epitaxial layer, wherein the second buried area is formed below and in contact with the surface contact region, thereby forming a vertical transistor in which the surface contact region and second buried area together form an emitter, the first buried area forms a base, and the epitaxial layer forms a collector.
 10. The electronic power device of claim 1 wherein the first and second buried layers are annular and the third and fourth buried layers are formed in the annular first and second buried layers, respectively.
 11. The electronic power device of claim 10 wherein the third and fourth buried layers are annular.
 12. An electronic power device integrated on a semiconductor substrate, comprising: an epitaxial layer formed on the semiconductor substrate; first and second buried layers formed in the epitaxial layer at a first level, the first buried layer forming an isolation region for a control transistor and the second buried layer forming a control region of a power transistor; third and fourth buried layers formed in the epitaxial layer at a second level, the third and fourth buried layers partially overlapping the first and second buried layers, respectively, the third buried layer forming a first conduction region of the control transistor and the fourth buried layer forming a conduction region of the power transistor; and first and second surface contact regions formed in the epitaxial layer, the first surface contact region forming a control region of the control transistor and the second surface contact region forming a second conduction region of the control transistor.
 13. The electronic power device of claim 12 wherein the first and second buried layers are annular and the third and fourth buried layers are formed in the annular first and second buried layers, respectively.
 14. The electronic power device of claim 13 wherein the third and fourth buried layers are annular.
 15. The electronic power device of claim 12 wherein the control transistor includes a vertical signal transistor and a lateral signal transistor.
 16. The electronic power device of claim 15 wherein the third buried layer forms a first conduction region of the vertical signal transistor and a control region of the lateral signal transistor, the first contact region forms a control region of the vertical signal transistor and first and second conduction regions of the lateral signal transistor, and the second contact region forms a second conduction region of the vertical signal transistor.
 17. The electronic power device of claim 12 wherein the first and second buried regions are formed at a depth of about 6 mm from an upper surface of the epitaxial layer and the third and fourth buried regions are formed at a depth of about 3-4 mm from the upper surface of the epitaxial layer.
 18. An electronic power device integrated on a semiconductor substrate, comprising: an epitaxial layer formed on the semiconductor substrate; first and second buried layers formed in the epitaxial layer at a first level, the first buried layer forming an isolation region for a control transistor and the second buried layer forming a control region of a power transistor; third and fourth buried layers formed in the epitaxial layer at a second level, the third and fourth buried layers partially overlapping the first and second buried layers, respectively, the third buried layer forming a first conduction region of the control transistor and the fourth buried layer forming a conduction region of the power transistor; and a surface contact region positioned in the epitaxial layer, wherein the second buried area is formed below and in contact with the surface contact region, thereby forming a vertical transistor in which the surface contact region and second buried area together form an emitter, the first buried area forms a base, and the epitaxial layer forms a collector.
 19. The power device of claim 18, wherein said first and third buried areas are placed at a depth of about 6 μm from an upper surface of the epitaxial layer and said second and fourth buried areas are placed at a depth of about 3-4 μm from the upper surface of the epitaxial layer.
 20. The power device of claim 18, further comprising: first, second, third, and fourth contact regions positioned in the epitaxial layer, the first and second contact regions extending from a surface of the epitaxial layer to contact opposite ends of the first buried area, and the third and fourth contact regions extending from the surface of the epitaxial layer to contact opposite ends of the third buried area.
 21. The power device of claim 20 wherein the second buried area is positioned between the first and second contact regions and the fourth buried area is positioned between the third and fourth contact regions.
 22. The power device of claim 18, further comprising first and second contact regions extending from a surface of the epitaxial region to contact opposite ends of the fourth buried region.
 23. The power device of claim 22, further comprising a doped region of the second conductivity type positioned in the epitaxial layer and between the first and second contact regions.
 24. The power device of claim 23, further comprising a doped region of the first conductivity type positioned in the doped region of the second conductivity type.
 25. The electronic power device of claim 18 wherein the first and second buried layers are annular and the third and fourth buried layers are formed in the annular first and second buried layers, respectively.
 26. The electronic power device of claim 25 wherein the third and fourth buried layers are annular. 